VLSI architectures for iterative decoders in magnetic recording channels

VLSI implementation complexities of soft-input soft-output (SISO) decoders are discussed, These decoders are used in iterative algorithms based on Tur bo codes or Low Density Parity Check (LDPC) codes, and promise significant bit error performance advantage over conventionally used partial-response m aximum likelihood (PRML) systems, at the expense of increased complexity, T his paper analyzes the requirements for computational hardware and memory a nd provides suggestions for reduced-complexity decoding and reduced control logic. Serial concatenation of interleaved codes, using an outer block cod e with a partial response channel acting as an inner encoder, is of special interest for magnetic storage applications.