Evaluation of ultra-low-k dielectric materials for advanced interconnects

The International Technology Roadmap for Semiconductors predicts that conti nued scaling of devices will require ultra-low-k materials with k values le ss than 2.5 for the 100 nm technology node and beyond. Incorporation of por osity into dense dielectrics is an attractive way to obtain ultra-low-k mat erials. Electrical and physical properties of ultra-low-k materials have be en characterized. Integration evaluations showed both feasibility and chall enges of porous ultra-low-k materials. This paper discusses issues and rece nt progress made with porous ultra-low-k material properties, deposition pr ocesses, characterization metrologies, and process integration.