1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus

A 1.6 Gb/s/pin 4-pulse-amplitude-modulated (PAM) multidrop signaling system has been designed, The motivation for multi-PAM signaling is discussed. Th e system uses single-ended + reference current-mode signaling with three de references for maximum bandwidth per pin. A testchip with six I/O pins was fabricated in 0.35-mum CMOS and tested in a 28-Omega evaluation system usi ng on-chip 2(10) pseudorandom bit sequence (PRBS) generator/checkers. Two d ifferent 4-PAM transmitter structures were designed and measured. A high-ga in windowed integrating input receiver with wide common-mode range was desi gned in order to improve signal-to-noise ratio when operating with smaller 4-PAM input levels, Gray coding allowed a folded preamplifier architecture to be used in the LSB input receiver to minimize area and power. In-system margins are measured via system voltage and timing shmoos with a master com municating with two slave devices.