Preparation of ramp-edge interface modified junctions for HTS SFQ circuits

We have studied the properties of ramp-edge interface modified Josephson ju nctions (IMJs) whose barriers are formed during the etching process and sub sequent annealing process, We already investigate the effect of process par ameters on junction characteristics (I-c, R-n). Furthermore, we obtain an e mpirical equation concerning the relationship between process parameters an d junction characteristics. We select accelerating voltage (V-acc) and etch ing time (t(etch)) for the control of I-c of IMJs and set the target value of I-c at 4.2K to 500 muA in this study. This target value can be realized by V-acc=500V and t(etch)=20min from the above-mentioned empirical equation . We prepare four different samples fabricated in the same conditions, and examine the reproducibility and controllability of I-c. The obtained I(c)s are very close to the target value, and the run-to-run spread is confined t o about 150 muA, The reproducibility and controllability of I-c are improve d compared to our previous data of junctions with artificial barriers.