We have proposed a cell-based design approach for rapid single flux quantum
(RSFQ) logic circuits. In our design approach, a binary decision diagram (
BDD) is used for representation of logical functions in order to reduce the
number of gates. We have made a standard cell library, which is composed o
f only five basic cells. We add one-junction Josephson transmission line (J
TL) to the edge of the input and the output node of some basic cells, by wh
ich no deterioration of the DC bias margin is observed for the connection o
f each cell. In the layout level, the size and the position of the input/ou
tput node of each cell are equalized. The standard cell circuits were fabri
cated by NEC 2.5kA/cm(2) and Hypres 1.0kA/cm(2) Nb standard process and the
y were tested at low speed.