A new concept for ultra-low power and ultra-high clock rate circuits

Compared with semiconductors, SFQ logic is very fast and dissipates extreme ly low power. But it does not approach the theoretical power dissipation as sociated with an SFQ switching event and single gate speed in complex circu its. For large circuits and systems, e,g., petaflops computing, we must red uce on-chip dissipation, achieve faster clocked logic operation, and increa se gate density. CMOS logic dissipates the energy required to switch a tran sistor pair and dissipates no power between switching events. We describe a new SFQ circuit concept that mimics CMOS to achieve ultra-low power dissip ation and ultra-high clock rates. This results in a physically compact, sel f-clocked, complementary logic (SCCL), in which clock distribution is frequ ency-independent. The basic element in this logic family is a simple two-ju nction comparator. Using TRW's 2kA/cm(2) Nb design rules, we simulated basi c digital components: shift register, AND, OR, and NOT at 20 GHz. We presen t the simulated and measured performance.