A third-order sine decimation filter was designed for a Sigma-Delta AID con
verter with a second-order modulator. The sine alter was formed from multis
tage decimation structure, which was constructed from the cascade connectio
n of third-order sine alters with a decimation factor of 2, A counter, cons
isting of single-flux-quantum (SFQ) toggle flip-flops (TFF) with destructiv
e readout, was used to reduce the circuit scale. The sine alter with a deci
mation factor of 2, which is the circuit that operates at the highest frequ
ency in a multistage decimation structure, operated up to the clock Frequen
cy of 18GHz in a circuit simulation. A sine Filter with a decimation factor
of 32 was calculated to require 6700 Josephson junctions that consume 1.9
mW.