Superconducting latching/SFQ hybrid RAM

Authors
Nagasawa, S Hasegawa, H Hashimoto, T Suzuki, H Miyahara, K Enomoto, Y
Citation
S. Nagasawa et al., Superconducting latching/SFQ hybrid RAM, IEEE APPL S, 11(1), 2001, pp. 533-536
Citations number
8
Categorie Soggetti
Apllied Physucs/Condensed Matter/Materiales Science
Journal title
IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY
ISSN journal
10518223 → ACNP
Volume
11
Issue
1
Year of publication
2001
Part
1
Pages
533 - 536
Database
ISI
SICI code
1051-8223(200103)11:1<533:SLHR>2.0.ZU;2-I
Abstract
We have developed a 256-bit superconducting latching/SFQ hybrid (SLASH) RAM block as the first step in developing a 16-Kbit SLASH RAM, which enables h igh-frequency clock operation up to 10 GHz The SLASH RAM is composed of ac- powered latching devices and de-powered SFQ devices. The 256-bit SLASH RAM block is composed of 16x16 matrix array of vortex transitional memory cells , SFQ-NOR decoders, latching drivers, latching sense circuits, and address buffers. The 256-bit SLASH RAM block chips were fabricated and tested. We c onfirmed that the 256-bit SLASH RAM block functioned successfully.