Pipelined DC-powered SFQ RAM

We present the design and test results of components for a superconductor C ryogenic Random Access Memory (CRAM). The 16-Kb RAM design consists of four 4-Kb sub-arrays (blocks) with a 400 ps access time (latency) and a 100 ps cycle time (throughput). Each 4-Kb RAM block comprises a row-accessed 32x12 8 memory cell array, bipolar line drivers, row decoders, and column sense c ircuits. The implementation of specially designed distributed Josephson Jun ctions in the sensing circuits reduces the overall size of the blocks and a llows the use of smaller de control currents.