Small scale integrated technology for HTS RSFQ circuits

A technology for fabrication of YBCO ramp junctions on a superconducting gr ound plane Is developed and evaluated. The technology is based on a two-lay er, S-I, structure or on a four-layer, S-I-S-I, structure grown in situ wit h YBCO superconductor and with multilayer Insulator of PBCO/STO/PBCO, Ramps for junctions, via connections and crossovers are formed by Ar ion milling under rotation and the ramp angle is less than 30 degrees for all directio ns. A 20-25 mm thick Ga-doped PBCO was used as a barrier for Josephson junc tions. One additional YBCO layer, for junction top electrodes and wiring, i s deposited and patterned Surface roughness of multilayers is characterized by AFM and is related to the Junction parameters, Transport properties of junctions, via connections and crossovers are evaluated.