Effects of parasitic capacitance in a magnetically-coupled voltage multiplier

Authors
Kiryu, S Maezawa, M Sasaki, H Hirayama, F Shoji, A
Citation
S. Kiryu et al., Effects of parasitic capacitance in a magnetically-coupled voltage multiplier, IEEE APPL S, 11(1), 2001, pp. 724-726
Citations number
5
Categorie Soggetti
Apllied Physucs/Condensed Matter/Materiales Science
Journal title
IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY
ISSN journal
10518223 → ACNP
Volume
11
Issue
1
Year of publication
2001
Part
1
Pages
724 - 726
Database
ISI
SICI code
1051-8223(200103)11:1<724:EOPCIA>2.0.ZU;2-C
Abstract
Effects of parasitic capacitance in a magnetically-coupled voltage multipli er (VM) are described. We found that parasitic capacitance between SQUIDs a nd JTLs in a VM decreases its operating margin. We also found that separati on of electric grounds for the output terminal of a VM from those for the J TLs is effective to improve the operating margin. Using this method, a 64-s tage VM was fabricated and well-defined output voltage was obtained.