Component development for a 16 Gb/s RSFQ-CMOS interface system

We have been developing an RSFQ-CMOS interface system The system consists o f three modules: a 1 to 32 bit DDST demultiplexer which converts a 16 Gb/s SFQ data input into a 32-channel 500 Mb/s output, asynchronous stacked-SQUI D amplifiers which amplify an SFQ data input into a 5 mV voltage level outp ut, and 77 K CMOS amplifiers which amplify a 5 mV voltage level input into a 5 V output at 500 MHz, We have implemented the asynchronous stacked-SQUID amplifier and the 77 K CMOS amplifier using the HYPRES 1 kA/cm(2) Nb proce ss and the ROHM 0.6 mum CMOS process, respectively, It was demonstrated tha t the 24-stage asynchronous stacked-SQUID amplifier amplifies an SFQ data i nput into a 2.0 mV voltage level at 600 MHz, The 77K CMOS amplifier was sho wn to amplify a 5 mV voltage level input into 5 V at 500 MHz from the simul ation, and a 175 mV voltage input into 3.5 V at 90 MHz from the experiment.