Submillimeter superconducting integrated receivers: Fabrication and yield

Fabrication procedure and yield analysis of superconducting integrated rece ivers is reported. These chip receivers, apart from the quasi-optical SIS m ixers, contain internal local oscillators and associated rf and de interfac es. Due to both complexity and design requirements of the integrated circui t, certain restrictions are applied to the standard Nb/Al/AlxOy/Nb SNEAP pr ocess. To obtain accurate area for micron-size SIS junctions and thickness for multi-layer SiO2 insulation, a few solutions and modifications were dev eloped. The possibility of transfering this fabrication process worldwide h as been proven experimentally.