A high density 4 kA/cm(2) Nb integrated circuit process

We have developed an improved 4 kA/cm(2) process technology that allows a s ignificant increase in circuit speed and density. Improved photoresist and dry etch processes have reduced critical dimension (CD) variation and impro ved CD linearity to below 1 mum These improvements have enabled a substanti al reduction in feature size and full utilization of existing photolithogra phy and etch tools. We have demonstrated wire pitch of 2.0 mum with less th an 0.1 mum CD loss. Minimum junction diameter and contact are 1.75 mum and 1.0 mum, respectively. Junctions, fabricated using a new barrier oxidation method with improved pressure control, have excellent I-V characteristics a nd array I-c nonuniformity less than 1.6% (1 sigma), We have demonstrated a 200 GHz, 12-stage divider circuit that is the fastest complex digital supe rconductor integrated circuit fabricated to date, With the present process tools, defects are the limiting factor to further increases in circuit dens ity and yield. In this paper, we discuss process improvements, electrical p erformance, defect reduction, and circuit performance.