Design of processor arrays for reconfigurable architectures

This paper deals with the design of processor arrays for regular algorithms . The design is constrained by limited implementation cost characterizing a reconfigurable architecture. The objective of the design is to minimize th e latency of the processor array. The presented approach to determine a sch eduling function leading to the minimal latency of the processor array is f ormulated as a linear program that incorporates 1) the selection of modules to be implemented in processors to execute operations of the algorithm, 2) the binding of operations to modules, 3) the computation of the number of registers, 4) the limitation of implementation cost for modules and registe rs, 5) the determination of the size of partitions that allows to match the limited implementation cost.