Data buffering and allocation in mapping generalized template matching on reconfigurable systems

Image processing algorithms for 2D digital filtering, morphologic operation s, motion estimation, and template matching involve massively parallel comp utations that can benefit from using reconfigurable systems with massive fi eld programmable gate array (FPGA) hardware resources. In addition, each al gorithm can be considered a special case of a "generalized template matchin g" (GTM) operation. Application performance on reconfigurable computer syst ems is often limited by the bandwidth to host or off chip memory. This pape r describes the GTM operation and characterizes the data allocation and buf fering strategies for the GTM operation on reconfigurable computers. Severa l mechanisms that support different levels of parallelism are proposed and summarized in the paper. Finally, the implementation of an infrared automat ic target recognition application on two commercial FPGA boards is used to demonstrate the various design options with different data allocation and b uffering mechanisms and the pruning of the design space based on the FPGA a rea and memory constraints.