V-SAT: A visual specification and analysis tool for system-on-chip exploration

We describe V-SAT, a tool for performing design space exploration of system -on-chip (SOC) architectures. The key components of V-SAT include EXPRESSIO N, a language for specification of the architecture, SIMPRESS, a simulator generator for analysis/evaluation of the architecture, and the V-SAT GUI fr ont-end for easy specification and detailed analysis. We give a brief overv iew of the components (EXPRESSION, SIMPRESS and GUI) and, using an example DLX architecture, demonstrate V-SAT's usefulness in exploration for an embe dded SOC codesign flow by specifying and evaluating several modifications t o the pipeline structure of the processor. We believe that V-SAT provides a powerful environment, both for early design space exploration, as well as for the detailed design of SOC architectures. (C) 2001 Elsevier Science B.V . All rights reserved.