Performance-constrained hierarchical pipelining for behaviors, loops, and operations

Behavioral specifications of DSP systems generally contain a number of nest ed loops. In order to obtain high date rates for such systems, it is necess ary to pipeline the system within the behavior, within the loop bodies, and also within the operations. In order to hierarchically pipeline a performa nce-constrained system, an important step consists of distributing the perf ormance constraint among the loops in such a manner that the constraint is satisfied and design cost; is minimized. This paper presents an algorithm f or propagating constraints and hierarchically pipelining, a given throughpu t-constrained system. Along with pipelining the algorithm schedules the ope rations within the loop bodies and selects components for them, with the ai m of minimizing cost while satisfying the constraint propagated to the loop body. Results demonstrate the necessity of pipelining across the three gra nularity levels in order to obtain high performance designs. They also demo nstrate the feasibility and quality of our approach, and indicate that it; may be efficiently used for synthesizing or estimating within system-level design.