Ta2O5/Silicon barrier height measured from MOSFETs fabricated with Ta2O5 gate dielectric

N-channel metal oxide semiconductor held effect transistors with Ta2O5 gate dielectric mere fabricated. The Ta2O5/silicon barrier height was calculate d using both the lucky electron model acid the thermionic emission model. B ased on the lucky electron model, a barrier height of 0.77 eV was extracted from the slope of the ln(I-g/I-d) versus ln(I-sub/I-d) plot using an impac t ionization energy of 1.3 eV, Due to the low barrier height, the applicati on of Ta2O5 gate dielectric transistors is limited to low supply voltage pr eferably less than 2.0 V.