Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric

Citation
Yc. Yeo et al., Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric, IEEE ELEC D, 22(5), 2001, pp. 227-229
Citations number
11
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE ELECTRON DEVICE LETTERS
ISSN journal
07413106 → ACNP
Volume
22
Issue
5
Year of publication
2001
Pages
227 - 229
Database
ISI
SICI code
0741-3106(200105)22:5<227:DGCTWU>2.0.ZU;2-O
Abstract
We report tile first demonstration of a dual-metal gate complementary metal oxide semiconductor (CMOS technology using titanium (Ti) and molybdenum (M o) as the gate electrodes for the N-metal oxide semiconductor field effect transistors (N-MOSFETs) and P-metal oxide semiconductor held effect transis tors (P-MOSFETs), respectively, The gate dielectric stack consists of a sil icon oxy-nitride interfacial layer and a silicon nitride (Si3N4) dielectric layer formed by a rapid-thermal chemical vapor deposition (RTCVD) process. C-V characteristics show negligible gate depletion. Carrier mobilities com parable to that predicted by the universal mobility model for silicon dioxi de (SiO2) are observed.