Sub-50 nm p-channel FinFET

High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-a ligned double-gate MOSFET structure (FinFET) is used to suppress the short- channel effects. This vertical double-gate SOI MOSFET features: 1) a transi stor channel which is formed on the vertical surfaces of an ultrathin Si fi n and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-aligned to each other and to the source/drain (S/D) r egions; 3) raised S/D regions; and 4) a short (50 nm) Si fin to maintain qu asi-planar topology for ease of fabrication. The 45-nm gate-length p-channe l FinFET showed an I-dsat of 820 muA/mum at V-ds = V-gs = 1.2 V and T-ox = 2.5 nm, Devices showed good performance down to a gate-length of 18 nm, Exc ellent short-channel behavior was observed. The fin thickness (correspondin g to twice the body thickness) is found to be critical for suppressing the short-channel effects, Simulations indicate that the FinFET structure can w ork down to 10 nm gate length, Thus, the FinFET is a very promising structu re for scaling CMOS beyond 50 nm.