Vertical n-channel MOSFETs for extremely high density memories: The impactof interface orientation on device performance

We investigate vertical n-channel MOSFETs fabricated at the sidewalls of et ched trenches. In general, these sidewalls can be nonplanar and incorporate different crystallographic orientations. Therefore, it is necessary to inv olve models for a variety of interface orientations in order to describe sc aled-down vertical devices. However, the crystalographic orientation of the interface has a strong impact on crucial device parameters such as gate ox ide thickness, carrier mobility, and interface trap density. For the first time, in this work a complete set of these parameters is inve stigated systematically for a wide range of different crystallographic orie ntations. Based on these parameters, the modeling of vertical MOSFETs featu ring a cylindrical geometry is demonstrated and verified by measurements. F urthermore, differences observed between vertical and planar devices of equ al parameters are deduced from interface properties related to the orientat ion of the sidewall.