1/f noise in CMOS transistors for analog applications

Noise measurements of the 1/f noise in PMOS and NMOS transistors for analog applications are reported under wide bias conditions ranging from subthres hold to saturation. Two "low noise" CMOS processes of 2 mum and 0.5 mum tec hnologies are compared and it is found that the more advanced process, with 0.5 mum technology, exhibits significantly reduced 1/f noise, due to optim ized processing. The input referred noise and the power spectral density (P SD) of the drain current 1/f noise are modeled in saturation as well as in subthreshold and are compared with the common empirical approaches such as the SPICE models. The results of this study are useful to the design and mo deling of 1/f noise of CMOS analog circuits.