A new model of gate capacitance as a simple tool to extract MOS parameters

Citation
L. Larcher et al., A new model of gate capacitance as a simple tool to extract MOS parameters, IEEE DEVICE, 48(5), 2001, pp. 935-945
Citations number
29
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON ELECTRON DEVICES
ISSN journal
00189383 → ACNP
Volume
48
Issue
5
Year of publication
2001
Pages
935 - 945
Database
ISI
SICI code
0018-9383(200105)48:5<935:ANMOGC>2.0.ZU;2-N
Abstract
This paper tackles the difficult task to extract MOS parameters by a new mo del of the gate capacitance that takes into account both poly-Si depletion and charge quantization and includes temperature effects. A new fast and it erative procedure, based on this simplified self-consistent model, will be presented to estimate simultaneously the main MOS system parameters (oxide thickness, substrate, and poly-Si doping) and oxide held, surface potential s at the Si/SiO2 and at the poly-Si/SiO2 interfaces. Its effectiveness will be demonstrated by comparing oxide field and oxide thickness to those extr acted by other methods proposed in the literature. Moreover, these methods are critically reviewed and we suggest improvements to reduce their errors, The agreement between CV simulation and experimental data is good without the need of any free parameter to improve the fitting quality for several g ate and substrate materials combinations. Finally, a simple law to estimate substrate and poly-Si doping in n+/n+ MOS capacitor from CV curves is prop osed.