On a dual-polarity on-chip electrostatic discharge protection structure

A novel dual-polarity on-chip electrostatic discharge (F,SD) protection str ucture is designed. The new ESD structure protects IC chips against ESD str essing in the two opposite directions. The ESD structure features symmetric deep-snapback current-voltage (I-V) characteristics, low-impedance active overcurrent discharging path, low holding voltage for over-voltage clamping , fast CSD response of similar to0.18 nS, low leakage (similar to pA), adju stable triggering voltage, and good scalability, It passes 14 KV HEM ESD za pping tests and achieves high ESD-performance-to-Si ratio of similar to 80 V/mum width, The new ESD structure reduces Si areas consumed by ESD protect ion units and ESD-induced parasitic effects significantly.