Quaternary static latch circuit

A new voltage-mode quaternary CMOS static latch circuit is presented. Only devices available in a standard digital CMOS fabrication technology-enhance ment-mode NMOS and PMOS transistors with single threshold voltage values-ar e used. No depletion-mode devices or special transistor threshold voltages are required. Three reference voltages and ground are used to define the lo gic levels. The operation of the quaternary latch is experimentally verifie d. Using data for a standard 2-micron digital CMOS fabrication technology, best- and worst-case on-chip setup and hold times are estimated, using simu lation, to be approximately 2.8 ns and 6.8 ns, respectively.