Performance and reliability improvement of low-power embedded flash memorywith shallow trench isolation structure

The design of programming/erasing (P/E) coupling ratios of advanced low-pow er embedded flash cells (working as an on/off switch) with a shallow trench isolation (STI) structure has been discussed to meet future performance re quirement. The reason that the stress-induced reliability degradation (SIRD ) problem becomes more severe when the STI structure is used in a low-power flash cell has also been clearly explained. In this paper, we suggest a dr ain (or source) side erase method for both lower-voltage operation and quic k data writing. This device must be operated at a suitable bias condition t o achieve the best reliability. For further improvement in the control and uniformity of the reliability performance, a modified STI module and modifi ed cell drain side engineering are proposed and verified on a 256 K NOR-typ e embedded low-power flash test vehicle.