Material analysis on degradation phenomena caused by hot carrier in 0.35 mu m WSi gate GaAs heterostructure insulated gate field effect transistors

From the viewpoint of device reliability of a 0.35 nm WSi Gate GaAs heteros tructure insulated gate field effect transistors, we studied the effect of the passivation film (SiON)/semiconductor (GaAs) interface stability on dev ice degradation. The degradation discussed here is characterized by an incr ease in the gate leakage current under a continuous reverse-voltage stress. We proposed a degradation model assuming the hole-trapping centers in the passivation film (SiON)/semiconductor (GaAs) interface. We found that this degradation did not occur after removing the SiON film and that a CF4 plasm a surface treatment after the WSi gate dry etching effectively suppressed t his degradation. These phenomena suggest the presence of hole-trapping cent ers in SiON/GaAs interface in the peripheral area of the WSi gate. To clari fy the effect of the CF4 plasma surface treatment, GaAs surfaces were inspe cted using physicochemical analyses. X-ray photoelectron spectroscopy and t otal reflection X-ray fluorescence revealed that CF4 plasma treatment remov ed the arsenic compounds, such as As2S3 and As2O3 which were formed on the GaAs surfaces during the gate dry etching with a gas mixture of SF6 and CHF 3. These arsenic compounds are considered to be the origin of hole-trapping centers, which cause this degradation. The physicochemical analyses fully support a previously proposed degradation mechanism. (C) 2001 The Electroch emical Society.