Design methodology of a low-energy reconfigurable single-chip DSP system

Authors
Wan, M Zhang, H George, V Benes, M Abnous, A Prabhu, V Rabaey, J
Citation
M. Wan et al., Design methodology of a low-energy reconfigurable single-chip DSP system, J VLSI S P, 28(1-2), 2001, pp. 47-61
Citations number
31
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
ISSN journal
13875485 → ACNP
Volume
28
Issue
1-2
Year of publication
2001
Pages
47 - 61
Database
ISI
SICI code
1387-5485(200105/06)28:1-2<47:DMOALR>2.0.ZU;2-2
Abstract
In this paper, we first present a reconfigurable architecture template for low-power digital signal processing, and then an energy conscious design me thodology to bridge the algorithm to architecture gap. The energy efficienc y of such an architecture and the effectiveness of the methodology are demo nstrated in case study implementations targeting baseband voice processing and digital signal processing.