Quantitative analysis of FPGA-based database searching

This paper reports two contributions to the theory and practice of using re configurable hardware to implement search engines based on hashing techniqu es, The first contribution concerns technology-independent optimisations in volving run-time reconfiguration of the hash functions; a quantitative fram ework is developed for estimating design trade-offs, such as the amount of temporary storage versus reconfiguration time. The second contribution conc erns methods for optimising implementations in Xilinx FPGA technology, whic h achieve different trade-offs in cell utilisation, reconfiguration time an d critical path delay; quantitative analysis of these trade-offs are provid ed.