Flip chip pin grid array (FC-PGA) packaging technology

As microelectronic products move toward greater levels of integration, incr easing functionality and enhanced performance, the complexity of packaging technology grows in direct proportion. With today's silicon processes evolu tion into finer and finer feature sizes, microprocessor designs are capable of achieving higher system clock speed. As a result, the level of integrat ion and the density of interconnect between processor chips and substrate h as been increased tremendously. The requirement brings with it an array of challenges for package design, substrate technology and assembly processes development. With the goal to provide highly integrated packaging at compet itive cost, Flip Chip Pin Grid Array package (FC-PGA) is proposed as an inn ovative socketable solution which includes the use of laser drilled blind / buried vias on PTH and SMT pin to ease routing and alleviate loop inductan ce. Its use of an existing PGA socket infrastructure expedites OEMs accepta nce to the newly designed package in various configurations. This paper describes key features of FC-PGA and technical challenges encoun tered in the FC-PGA package design/validation and packaging processes devel opment; such as selection of solder composition and optimization of SMT pin technology, resolution to via delamination and flip chip solder bump non-w et resulting in electrical failure. FC-PGA package design and process devel opment efforts have successfully demonstrated the feasibility of high densi ty flip chip interconnect on organic substrate and high speed bus functiona lity with low cost, high yielding, manufacturable and reliable packaging so lution, which has been utilized in Pentium (TM) III microprocessors. It is expected this cost effective FC-PGA represents a shift in packaging technol ogy that offer great advantages for future products and represents a signif icant milestone in organic packaging technology.