A cutting algorithm for optimizing the wafer exposure pattern

Semiconductor manufacturing industry competes bg increasing yield and lower ing die costs, thereby taking advantage of significant capital investments, Many studies focus on defect reduction to improve yield rate. However, the problem of optimizing wafer exposure patterns has received little attentio n. In this paper, given the specific patterning constraints, we develop a t wo-dimensional (2-D) cutting algorithm to maximize the gross die yields of the eight-inch wafer and larger circular wafers, The empirical results that we implemented in a wafer fabrication factory in Taiwan validate the pract ical viability of this approach, Similar approaches can readily be applied to other safer patterning.