Impact of small process geometries on microarchitectures in systems on a chip

Process effects in deep-submicrometer geometrics are expected to change the physical organization, or microarchitecture, of integrated circuits. The f actor that is expected to primarily impact integrated circuit microarchitec tures is increasing delays in interconnect. We believe that, to properly mi croarchitect integrated circuits in small process geometrics, it is necessa ry to get as detailed a picture as possible of the effects and then to draw conclusions about changes in microarchitecture. To this end, in this paper , we describe a comprehensive approach to accurately characterizing the dev ice and interconnect characteristics of present and future process generati ons. This approach uses a detailed extrapolation of future process technolo gies to obtain a realistic view of the future of circuit design. We then pr oceed to quantify the precise impact of interconnect, including dynamic del ay due to noise, on the performance of high-end integrated circuit designs. Having determined this, we then reconsider the impact of future processes on integrated-circuit design methodology. We determine that local interconn ect effects can be managed through a deep-submicrometer design hierarchy th at uses 50K-100K gate modules as primitive building blocks. In light of this new system-on-a-chip microarchitecture, we then examine gl obal interconnect issues. Our results indicate that, while global communica tion speeds will necessarily be lower than local clock speeds. Internationa l Technology Roadmap for Semiconductors expectations should be attainable t o the 0.05-m technology generation. Achieving these high clock speeds (10 G Hz local clock) will be aided by the use of a newly proposed routing hierar chy that limits interconnect effects at each level of a design (local, isoc hronous, and global). In addition, key components of the interconnect archi tecture of the future include fat ( or unscaled) global wires, intelligent repeater and shield wire insertion, and efficient packaging technologies.