On-chip wiring design challenges for gigahertz operation

This paper reviews the status of present day on-chip wiring design methodol ogies and understanding. A brief explanation is given of the fundamental tr ansmission-line properties that should be considered for accurate predictio n of crosstalk, common-mode noise and clock skew. The deficiencies of RC-ci rcuit representation are highlighted and design guidelines are given for us ing modeling and simulation techniques that have been previously used for p ackage interconnections. Such techniques are believed to teach designers ho w to make better use of available technologies and help them architect syst ems that operate with many-GHz clock rates.