The challenge of signal integrity in deep-submicrometer CMOS technology

Advances in interconnect technologies, such as the increase in the number o f metal layers, stacked vias, and the reduced routing pitch, hale played a key role to continuously improve integrated circuit density and operating s peed. However, several parasitic effects jeopardize the benefits of scale-d own. Understanding and predicting interconnect behavior is vital for design ing high-performance integrated circuit design. Our paper first reviews the interconnect parasitic effects and examines their impact on circuit behavi or and their increase due to lithography eduction, with special emphasis on propagation delay, lateral coupling, and crosstalk-induced delay. The prob lem of signal integrity characterization is then discussed. In our review o f the different well-established measurement methodologies such as direct p robing, S-parameters, e-beam sampling, and on-chip sampling, we point out w eaknesses, frequency ranges, drawbacks, and overall performances of these t echniques. Subsequently, the on-chip sampling system is described. This fea tures a precise time-domain characterization of the voltage waveform direct ly within the interconnect and shows its application in the accurate evalua tion of propagation delay, crosstalk, and crosstalk-induced delay along int erconnects in deep-submicrometer technology. The sensor parts are described in detail, together with signal integrity patterns and their implementatio n in 0.18-mum CMOS technology Measurements obtained with this technique are presented. In the third part, we discuss the simulation issues, describe t he two-and three-dimensional interconnect modeling problems, and review the active device models applicable to deep-submicrometer technologies in orde r to agree on measurements and simulations. These studies result in a set o f guidelines concerning the choice of interconnect models. The last part ou tlines the design rules to be used by designers and their implementation wi thin computer-aided design (CAD) tools to achieve signal integrity complian ce. From a 0.18-mum technology are derived critical variables such as cross talk tolerance margin, maximum coupling length, and the criteria for adding a signal repeater: From these, values for low-dielectric and copper interc onnects hale been selected.