An analytical method for the thermal layout optimisation of multilayer structure solid-state devices

In this paper an analytical method for the electrothermal solution to the n on-linear 3-D heat flow equation for multilayer structure electronic device s is proposed. Compared with previous models presented in literature, it is general and call be easily applied to a large variety of integrated device s, provided that their structure can be represented as an arbitrary number of superimposed layers with a 2-D embedded thermal source, so as to include the effect of the package. The proposed method is independent of the speci fic physical properties of the layers, hence GaAs MESFETs and HEMTs as well as silicon and silicon-on-insulator MOSFETs and heterostructure LASERs can be analysed. Moreover, it takes into account the dependence of the thermal conductivity of all the layers on the temperature; the heat equation is so lved coupled with the device current-voltage relation in order to give phys ical consistence to the ex perimental evidence that a temperature increase causes a degradation of the electrical performances and that the electrical power is not uniformly distributed. (C) 2001 Elsevier Science Ltd. All rig hts reserved.