Instruction cache organisation for embedded low-power processors

A low-power I-cache architecture is proposed that is appropriate for embedd ed low-power processors, Unlike existing schemes, the proposed organisation places an extra small cache in parallel alongside the L1 cache. Since it a llows simultaneous accesses to both caches, the proposed scheme introduces Little performance degradation. Using simple hardware logic (for sequential accesses) and a compiler transformation (for loop accesses), most L1 cache requests are served by a small each. so that the amount of energy consumed by the L1 cache is significantly reduced. Experimental results show that f or the SPEC95 benchmarks. the proposed organisation reduces the energy-dela y product on average by 67.2% over a conventional cache design and 16.8% ov er the filter cache design.