Switching activity evaluation of CMOS digital circuits using logic timing simulation

The degradation delay model is applied to accurately estimate the switching activity in CMOS digital circuits. The model overcomes the limitations of conventional gate-level logic simulators to handle the propagation of glitc hes, a main sourer of switching activity. Model results of a four-bit multi plier are within 4% with respect to HSPICE. while Verilog overestimations a re up to 68%.