Lifting factorization-based discrete wavelet transform architecture design

Citation
Wq. Jiang et A. Ortega, Lifting factorization-based discrete wavelet transform architecture design, IEEE CIR SV, 11(5), 2001, pp. 651-657
Citations number
24
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY
ISSN journal
10518215 → ACNP
Volume
11
Issue
5
Year of publication
2001
Pages
651 - 657
Database
ISI
SICI code
1051-8215(200105)11:5<651:LFDWTA>2.0.ZU;2-X
Abstract
In this paper, tao new system architectures, overlap-state sequential and s plit-and-merge parallel, are proposed based on a novel boundary postprocess ing technique for the computation of the discrete wavelet transform (DWT). The basic idea is to introduce multilevel partial computations for samples near data boundaries based on a finite state machine model of the DWT deriv ed from the lifting scheme. The key observation is that these partially com puted (lifted) results can also be stored back to their original locations and the transform can be continued anytime later as long as these partial c omputed results are preserved. It is shown that such an extension of the in -place calculation feature of the original lifting algorithm greatly helps to reduce the extra buffer and communication overheads, in sequential and p arallel system implementations, respectively. Performance analysis and expe rimental results show that, for the Daubechies (9,7) wavelet filters, using the proposed boundary postprocessing technique, the minimal required buffe r size in the line-based sequential DWT algorithm [1] is 40% less than the best available approach. In the parallel DWT algorithm me show 30% faster p erformance than existing approaches.