In this paper, we describe area and power reduction techniques for a low-la
tency adaptive finite-impulse response filter for magnetic recording read c
hannel applications. Various techniques are used to reduce area and power d
issipation while speed and latency remain as the main performance criteria
for the target application, The proposed parallel transposed direct form ar
chitecture operates on real-time input data samples and employs a fast, low
-area multiplier based on selection of radix-8 premultiplied co-efficients
in conjunction with one-hot encoded bus leading to a very compact layout an
d reduced power dissipation. Area, speed, and power comparisons with other
low-power implementation options are also shown, The proposed filter has be
en fabricated using a 0.18-mum L-effective CMOS technology and operates at
550 MSamples/s. Trading off biter latency to improve speed is also discusse
d.