An automated process for compiling dataflow graphs into reconfigurable hardware

We describe a system, developed as part of the Cameron project, which compi les programs written in a single-assignment subset of C called SA-C into da taflow graphs and then into VHDL, The primary application domain is image p rocessing, The system consists of an optimizing compiler which produces dat aflow graphs and a dataflow graph to VHDL translator. The method used for t he translation is described here, along with some results on an application . The objective is not to produce yet another design entry tool, but rather to shift the programming paradigm from HDLs to an algorithmic level, there by extending the realm of hardware design to the application programmer.