First implementation of the MEPHISTO binary readout architecture for stripdetectors

Today's front-end readout chips for multi-channel silicon strip detectors u se pipeline-like structures for temporary storage of hit information until al,rival of a trigger signal. This approach leads to large-area chips when long trigger latencies are necessary. The h MEPHISTO architecture uses a di fferent concept. nit strips are identified in real time and only the releva nt binary hit information is stored in FIFOs. For the typical occupancies i n LHC detectors of approximate to 1 hit per clock cycle this architecture I L quires less than half the chip area of a typical binary pipeline. This re duces the system cost considerably. At a lower data I-ate, operation with v ery long trigger latencies or even without any trigger is possible due to t he real-time data sparsification. The Mephisto II architecture is presented and the expected performance is discussed. (C) 2001 Elsevier Science B.V. All rights reserved.