We plc sent the design of the Global Calorimeter Trigger processor for the
CMS detector at LHC. This is a fully pipelined processor system which colle
cts data from all the CMS calorimeters and produces summary information use
d in forming the Level-1 trigger decision for each event. The design in bas
ed on the use of state-of-the-art reconfigurable logic devices (FPGAs) and
fast data links. We present the results of device testing using a low-laten
cy pipelined sort algorithm, which demonstrate that an FPGA can be used to
perform processing previously foreseen to require custom ASICs. Our design
approach results in a powerful, flexible and compact processor system. (C)
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