Low-power system-level design of VLSI packet switching fabrics

System-level design of packet switching fabrics focuses on performance metr ics and rarely considers the physical requirements that are usually address ed later at the circuit-level, However, low-power dissipation has become a major requirement in such fabrics dictated by the requirements of emerging applications and by the recent advances in fabrication and VLSI technologie s. This paper proposes a framework for system-level design of packet switch ing fabrics that integrates performance specifications along with physical requirements and constraints. Moreover, realistic traffic models are used t o derive the transition activity and the packet arrival and departure event s needed for power estimation. physical requirements are defined by an arch itectural model for power dissipation based on the stochastic traffic model , models for silicon area, chip count, and input-output pins, which provide a complete system-level specification of the fabric, Performance constrain ts are also derived from the stochastic traffic model. This framework formu lates and solves the power optimization problem subject to those physical a nd performance constraints as an integer nonlinear optimization problem. Th e results obtained emphasize the importance of traffic-driven system-level optimization and show the efficiency of this framework as a system-level de sign space exploration tool.