Interconnect performance estimation models for design planning

This paper presents a set of interconnect performance estimation models for design planning with consideration of various effective interconnect layou t optimization techniques, including optimal wire sizing, simultaneous driv er and wire sizing, and simultaneous buffer insertion/sizing and wire sizin g. These models are extremely efficient, yet provide high degree of accurac y. They have been tested on a wide range of parameters and shown to have ov er 90% accuracy on average compared to running best-available interconnect layout optimization algorithms directly, As a result, these fast yet accura te models can be used efficiently during high-level design space exploratio n, interconnect-driven design planning/synthesis, and timing-driven placeme nt to ensure design convergence for deep submicrometer designs.