Design and efficient implementation of a modulated complex lapped transform processor using pipelining technique

This paper presents the design of a modulated complex lapped transform (MCL T) processor and its complex programmable logic device (CPLD) implementatio n. The MCLT is a 2x oversampled DFT filter bank: it performs well in applic ations that require a complex filter bank, such as noise reduction and acou stic echo cancellation. First, we show that the MCLT can be mapped to a Fas t Fourier Transform (FFT). Then efficient implementation for fast MCLT comp utation is realized on the CPLD hardware using pipelining techniques. Detai led circuit design for the MLCT processor is presented, as well as timing d iagrams for design verification and performance evaluation.