A 32-bit RISC microprocessor with DSP functionality: Rapid prototyping

We have designed a 32-bit RISC microprocessor with 16-/32-bit fixed-point D SP functionality. This processor, called YD-RISC, combines both general-pur pose microprocessor and digital signal processor (DSP) functionality using the reduced instruction set computer (RISC) design principles. It has funct ional units for arithmetic operation, digital signal processing (DSP) and m emory access. They operate in parallel in order to remove stall cycles afte r DSP or load/store instructions, which usually need one or more issue late ncy cycles in addition to the first issue cycle. High performance was achie ved with these parallel functional units while adopting a sophisticated fiv e-stage pipeline structure. The pipelined DSP unit can execute one 32-bit m ultiply-accumulate (MAC) or 16-bit complex multiply instruction every one o r two cycles through two 17-b x 17-b multipliers and an operand examination logic circuit. Power-saving techniques such as power-down mode and disabli ng execution blocks allow low power consumption. In the design of this proc essor, we use logic synthesis and automatic place-and-route. This top-down approach shortens design time, while a high clock frequency is achieved by refining the processor architecture.