A simulator to calculate slip length during thermal processes on the basis
of dislocation kinetics was developed. Using the simulator, slip length dur
ing the thermal process of 300 mm wafers was calculated. From the results o
f the calculations it was clarified that: (1) control of the ramping rate a
bove 1000 degreesC is important to avoid slip generation; (2) when the wafe
r spacing is 9.5 or 6.75 mm, slip dislocation will generate during the proc
ess at a ramping rate greater than 1.8 or 1.3 degreesC/min, respectively; a
nd (3) slip length decreased using a ring-like support instead of a convent
ional four-point support. The generation of punched-out dislocations and sl
ip in a heavily boron-doped p + epitaxial substrate was also examined by in
dentation tests and thermal stress tests. It was found that the generation
of dislocations could be reduced compared with that of p/p - wafers by usin
g p + epitaxial substrates. (C) 2001 Elsevier Science B.V. All rights reser
ved.