Enhancement of gettering efficiencies of different silicon substrates during a 0.18 mu m LTB CMOS process simulation - Stratigraphy by a novel chemical ultra-trace depth-profiling

We have performed a gettering efficiency (GE) test at different stages in a 0.18 mum LTB CMOS process simulation with maximal temperatures of 1000 deg reesC. Four sorts of wafer substrates (epi, polished) were processed to the point before the step to be studied and then contaminated with 5 X 10(12) atoms/cm(2) Cu or Ni with a spin-on technique that was optimized for reprod ucibility. Afterwards, the wafers were process simulated and analyzed by IC P-MS in combination with a novel chemical depth-profiling procedure. Althou gh none of the wafers showed detectable BMDs by preferential etching and FT IR measurements, BMDs could be found by LST measurements. Epitaxial p/p + w afers exhibited an outstandingly high GE for Cu at each studied process ste p due to segregation gettering by the heavily boron doped substrate. Polish ed wafers showed a lower GE which increased with the process time. Thus, Cu gettering was a function of the size of oxygen precipitates. On the contra ry, Ni gettering was not enhanced in epi wafers compared to the polished wa fers. Also, no segregation gettering is assumed for Ni, however, a higher i nitial oxygen concentration led to a higher GE. Thus, Ni gettering is stron gly influenced by the oxygen precipitate size, too. A more stable Cu and Ni gettering was found with BMD-densities of 10(9) cm(-3) measured by LST, al though preferential etching and FTIR measurements were below the detection limit. (C) 2001 Elsevier Science B.V. All rights reserved.