Data and memory optimization techniques for embedded systems

We present a survey of the state-of-the-art techniques used in performing d ata and memory-related optimizations in embedded systems. The optimizations are targeted directly or indirectly at the memory subsystem, and impact on e or more out of three important cost metrics: area, performance, and power dissipation of the resulting implementation. We first examine architecture-independent optimizations in the form of code transformations. We next cover a broad spectrum of optimization techniques that address memory architectures at varying levels of granularity, rangin g from register files to on-chip memory, data caches, and dynamic memory (D RAM). We end with memory addressing related issues.